to operate and then to reset or vice-versa ![](/iev/iev.nsf/FiguresShared/1-60050-447-Ed2-IS-CDV-Fig1-en-4web/$file/1-60050-447-Ed2-IS-CDV-Fig1-en-4web.png)
Figure 1 – Explanatory diagram for operate condition ![](/iev/iev.nsf/FiguresShared/1-60050-447-Ed2-IS-CDV-Fig2a-en-4web/$file/1-60050-447-Ed2-IS-CDV-Fig2a-en-4web.png)
a) Output circuits are fully reset before all internal status are reset ![](/iev/iev.nsf/FiguresShared/1-60050-447-Ed2-IS-CDV-Fig2b-en-4web/$file/1-60050-447-Ed2-IS-CDV-Fig2b-en-4web.png)
b) Output circuits are fully reset after all internal status are reset Figure 2 – Explanatory diagram for reset condition
|